I2C bus control for isolating selected IC&#39;s for fast I2C bus communication

ABSTRACT

A system, method, and apparatus are provided for selectively isolating particular ICs on an I 2 C bus system. Selective isolation of particular ICs allows the particular isolated ICs to communicate with each other and/or with other components at a data transfer rate that is greater than the data transfer rate for the I 2 C bus system. A switch is operative in one mode to selectively isolate an auxiliary or separate I 2 C portion containing the ICs to be isolated and operative in another mode to allow the auxiliary I 2 C portion to be part of the main I 2 C bus sys portion tem. Proper pull-up resistors associated with the switch aid in allowing a faster data transfer rate by speed up of the low to high transition for operation of the isolated ICs.

This application claims the benefit, under 35 U.S.C. § 365 ofInternational Application PCT/US01/48036, filed Dec. 11, 2001, which waspublished in accordance with PCT Article 21(2) on Jun. 27, 2002 inEnglish and which claims the benefit of U.S. patent application No.60/256,966, filed Dec. 20, 2000.

The present invention relates to the I²C bus/protocol and integratedcircuits that utilize the I²C bus/protocol, and more particularly, toauxiliary circuits for use with the I²C bus/protocol and integratedcircuits associated therewith.

Integrated circuits (“ICs”) are extensively used in today's electronicdevices. ICs are typically designed to perform particular functions, andas such, many different ICs are generally necessary for a modernelectronic device to operate. The ICs of a modern electronic device mustbe able to cooperate with one another in order to orderly communicate(receive and/or transmit data/information) with one another.

Cooperation and communication in an IC environment includes the abilityof an IC to send data/information to other ICs typically in response toa query signal from another IC and/or to receive data/information fromother ICs. This is typically achieved by providing a communication linkor channel between the ICs. One way to efficiently provide thecommunication link is to connect the ICs together via a bus structure. Abus structure is essentially a common communication channel for aplurality of ICs in an electronic device.

One well known bus system/structure is the Inter Integrated Circuit busor the I²C bus (interchangeably, the I2C bus). The I²C bus systemoperates on an I²C protocol that allows a plurality of ICs to beconnected to and be in communication with one another over a common,structured bus. The I²C bus system was developed by PhillipsSemiconductor to provide a way to connect (i.e. provide communicationbetween) a central processing unit (CPU) and associated peripheral ICswithin a television environment. The I²C bus system has been usedextensively in consumer electronic devices. Because of this, variousIC's are designed for and include the necessary elements for operatingin an I²C environment.

More specifically, the I²C bus system is a serial bus system. Inimplementing the I²C bus, each IC, (i.e. a device, driver, memory, orcomplex function IC/chip), or the like is assigned a unique address. Aparticular IC in the I2C system can then send and/or receive datato/from a second IC by using the address of the second IC. Inmaintaining the integrity of I²C, when a new IC is developed, thedesigner must apply for and obtain a unique IC address from the I²Cauthorizing/issuing entity (i.e. Phillips Semiconductor). This allowsthe I²C system to grow as more types of addressable devices/ICs areuniquely registered. The unique IC address is then hardwired internal tothe IC. Phillips Semiconductor maintains these addresses (otherwiseknown as “slave addresses”) in a registry, or the like, to assureintegrity of the assigned addresses.

The I²C system, however, is generally constrained to transfer dataaccording to a set protocol at a set clock speed. The main controller ICof the I²C system sets the transfer rate or speed (i.e. clock rate orbus speed). Thus all ICs connected to a particular I²C bus mustcommunicate at the same speed, or data transfer rate. However, it may bedesirable to allow some ICs to communicate at different clock speedunder certain conditions.

For example, some ICs for certain consumer electronics applications mayhave power up I²C routines that load data from a memory at a given datatransfer rate that may be different than the I²C bus speed set by themain micro in normal conditions of the I²C system. For example, liquidcrystal on silicon displays for certain video display systemsmanufactured by Thomson Consumer Electronics, Inc. of Indianapolis,Ind., use ICs manufactured by Three-Five Systems, Inc, of Tempe, Ariz.The Three-Five Systems' ICs have a hard-coded power up I²C routine thatloads the three Application Specific Integrated Circuits (“ASICs”) froma 64K EEPROM (memory) at 400 KHz bus speed. With multiple ICs, includingthe Three-Five Systems' ICs on a given I²C bus branch, a suitablepull-up does not exist that allows the fast rise times required by thepower up I²C routine and, with series resistance on the I²C bus, norallows all of the I²C devices to pull the control lines effectively tothe low state. In view of the above, it is desirable to provide a busarrangement that allows particular ICs in an I²C system to communicateat speeds different than the communication speed of other ICs within anI²C system.

The present invention is a system, method, and apparatus for isolatingselect integrated circuits in a digital bus system. Particularly, thepresent invention is a system, method and apparatus for selectivelyisolating one or more integrated circuits disposed on various portionsof an I²C bus system for a predetermined period of time. Moreparticularly, the present invention is a system, method and apparatusfor selectively isolating a plurality of integrated circuits of an I²Cbus system for allowing the isolated integrated circuits to communicateat a data transfer rate that is different than the data transfer rate ofthe I²C bus system. Once isolated, the selected plurality of integratedcircuits may communicate with each other independent of the remainder ofthe I²C bus system integrated circuits.

In one form, the present invention is an apparatus for selectivelyisolating a portion of an I²C bus system. The system includes a main I²Cbus portion, a main controller IC in communication with the main I²C busportion, an auxiliary I²C bus portion, and a switch interposed betweenthe main I²C bus portion and the auxiliary I²C bus portion and incommunication with the main controller IC. The switch is operative undercontrol of the main controller IC to isolate the auxiliary I²C busportion from the main I²C bus portion. The switch also provides controlof the pull up is current for the auxiliary I²C bus portion.

In another form, the present invention is a method for selectivelyisolating a portion of an I²C bus system. The method includes the stepsof: (a) providing a control signal to a switch interposed between a mainI²C bus portion having a main data line and a main clock line, and anauxiliary I²C bus portion having an auxiliary data line and an auxiliaryclock line, the switch having a first mode of operation in which theauxiliary data line is in communication with the main data line, and theauxiliary clock line is in communication with the main clock line, and asecond mode of operation in which the auxiliary data line is isolatedfrom the main data line, and the auxiliary clock line is isolated fromthe main clock line; and (b) utilizing the control signal to cause theswitch to operate in either the first mode of operation or the secondmode of operation.

In yet another form, the present invention is a television signalreceiver. The television signal receiver includes a main I²C busportion, a master controller IC in communication with the main I²C busportion, a first plurality of I²C compatible ICs in communication withthe main I²C bus portion, an auxiliary I²C bus portion, a secondplurality of I²C compatible ICs in communication with the auxiliary I²Cbus portion, and a switch interposed between the main I²C bus portionand the auxiliary I²C bus portion, and in communication with the mastercontroller IC. The switch is under control of the master controller ICto selectively isolate the auxiliary I²C bus portion and thus the secondplurality of I²C compatible ICs from the main I²C bus portion for apredetermined period of time.

The present invention allows the isolation of particular or select I²Cportions or devices, while at the same time providing low impedancepull-ups (resistors). In turn, higher current pull-ups (resistors) allowoperation of the isolated ICs at a higher speed. When the isolated ICsare returned to the main I²C bus, the resistors are out of the auxiliarycircuit. During the time that the isolated ICs are reading data, themain micro of the I²C system can configure other I²C ICs on the I²C bus,thus saving start-up time.

The above-mentioned and other features and advantages of this invention,and the manner of attaining them, will become more apparent and theinvention will be better understood by reference to the followingdescription of all exemplary embodiment of the invention taken inconjunction with the accompanying drawings, wherein:

FIG. 1 is a diagram of an exemplary system comprising a plurality of ICsin communication with one another via the I²C bus/protocol;

FIG. 2 is a block diagram representation of an apparatus suitable forimplementing the present invention;

FIG. 3 is an exemplary circuit in accordance with the principles of thepresent invention;

FIG. 4 is a timing chart for various signals of the circuit of FIG. 3;and

FIG. 5 is a flow chart of the steps performed by the exemplary system ofthe present invention.

Corresponding reference characters indicate corresponding partsthroughout the several figures.

Referring now to FIG. 1, there is depicted a system, generallydesignated 10, that represents a system in which a plurality of ICs areconnected together and in communication with each other via a busstructure.

In particular, system 10 is an I²C bus/protocol system. I²C system 10includes controller IC 12 connected to and in communication with an I²Cbus, generally designated 18. Controller IC 12 may be referred to as themain IC, main micro, or the like, and is operative to initiate datatransfers on bus 18. Controller IC 12 may be a microprocessor, a CPU orthe like. I²C system 10 further includes a plurality of slave ICs,generally designated 20 (with various subscripts), that are connected toand in communication with the various other ICs via I²C bus 18.

I²C bus 18 consists of Serial Clock line (SCL) 14 and Serial Data line(SDA) 16. SCL line 14 is coupled to an I/O pin of main controller IC 12and to an I/O pin of each slave IC 20 for supplying a serial clocksignal to each slave IC 20. SDA line 16 is coupled to another I/O pin ofthe main controller IC 12 and to another I/O pin of each slave IC 20 fordata transfer and general communication. Data transfer between the ICsis accomplished at a certain predetermined data rate (50 KHz).

Although SCL line 14 is a bi-directional line, the main controller IC 12controls/generates the system clock and thus SCL line 14 has asingle-headed arrow to designate the nature of data flow on the clocksignal line. SDA line 16 is also a bi-directional line and thus has adouble-headed arrow to designate the nature of data flow on the serialdata line. Each slave ICs 20 is operative to receive protocol commandsfrom main controller IC 12 and to respond appropriately.

In order to communicate with and between the plurality of slave ICs 20,each slave IC 20 is assigned a unique address. The unique address ishardwired into the respective slave IC 20, typically within an I²C businterface section. The internal address of each slave IC 20 is thusfixed. Some of slave ICs 20 have only one fixed address, while someslave ICs may have more than one fixed address, typically due, at leastin part, to having a plurality of internal I²C bus interface sections,each of which has a previously assigned I²C address.

Also, each slave IC 20 communicates with main controller IC 12 at a setI²C data rate, typically 50 KHz. Main controller IC 12 and slave ICs 20also typically have a start-up routine that follows the standard I²Cprotocol.

In sum, the I²C system is a two-wire, bi-directional bus system thatpermits any two ICs to communicate with each other via bus 18 at any onetime. Main controller IC 12 serves in a “master” mode of operation,initiates a data transfer on bus 18 and generates clock signals thatpermit the data transfer. Slave ICs 20 serve in a “slave” mode ofoperation when the slave IC 20 is being operated on or communicated toby main controller IC 12, whereby a particular slave IC 20 is instructedto either send or receive data. SCL line 14 propagates clock signals onI²C bus 18 from the main controller IC 12 to slave the ICs 20. Each maincontroller IC 12 (as there can be more than one main controller IC)generates its own clock signals when transferring data on bus 18. Thesecond bi-directional wire of I²C bus 18, i.e. the serial data line(SDA) 16, transfers data using eight bit serial transactions. A ninthbit is typically utilized as an acknowledgement bit.

When both SCL line 14 and SDA line 16 are held “HIGH” or logic “1”, nodata can be transferred between two ICs. A HIGH to LOW (logic “0”)transition on SDA line 16, while SCL line 14 is HIGH, indicates a STARTcondition for the exchange of data bits. Conversely, a LOW to HIGHtransition on SDA line 16, while SCL line 14 is HIGH, defines a STOPcondition. Main controller IC 12 generates one clock pulse for each databit transferred on SDA line 16, and the HIGH or LOW state of SDA line 16can only change when the clock signal on SCL line 14 is in a LOW state.

It should be appreciated that system 10 of FIG. 1 is only exemplary ofan environment/application in which the present invention may beutilized. Preferably, the present invention is applicable to and used inany system of ICs that utilize the I²C protocol/bus structure/system.However, the present invention may be used in other similar protocol/busstructures/systems. The type of ICs, and IC systems in which the presentinvention is utilized may take many forms and/or perform many functions.The exemplary system 10 of FIG. 1, may advantageously be part of theoperation circuitry of a television signal processing device.

Referring to FIG. 2, there is depicted a block diagram representing anexemplary device in which I²C system 10 and the present invention may beused. FIG. 2 shows a consumer electronic device, generally designated30, that may be a television signal receiver/processor, set-top box,satellite receiver, or any type of consumer electronic device thatutilizes a digital bus protocol system such as the I²C system describedabove.

Consumer electronic device 30 includes a main I²C bus and I²C componentsas generally described above with reference to FIG. 1 and I²Ccomponents, generally designated 32. In accordance with an aspect of thepresent invention, consumer electronic device 30 includes auxiliary ICswithin auxiliary circuitry or circuitry/logic, generally designated 34.Auxiliary ICs 34 are preferably I²C compatible. Auxiliary ICs 34 areconnected to and in communication with the main I²C bus and I²Ccomponents 32 via a switch, switch circuitry/logic, or the like 36(collectively, switch 36). Switch 36 is operative to selectively connectthe auxiliary ICs with the main I²C system in one mode thereof, and toselectively isolate the auxiliary ICs from the main I²C system inanother mode.

More particularly, auxiliary ICs 34 are operative to communicate via adata transfer rate (i.e. bus rate) that is greater than the bus rate ofthe main I²C bus and I²C components (i.e. at a high data transfer rate).As such, switch 36 is operative to isolate or disconnect auxiliary ICs34 from main I²C bus/system 32 when it is necessary for auxiliary ICs 34to communicate or perform an operation or function using high datatransfer rate rather than the data rate of the main I²C system or whenan auxiliary IC, or ICs, communicate or perform an operation or functionwithin the circuitry/logic of auxiliary system 34.

In accordance with the present invention, device 30 operates in one of aplurality of modes. During a first state, or mode, switch 36 allowsauxiliary ICs 34 to be isolated from the main I²C bus. The isolationallows the auxiliary ICs to communicate between each other and any otherdevices associated with auxiliary circuitry/logic 34. During a secondstate or mode, switch 36 operatively connects auxiliary ICs/circuitry 34with main I²C bus/system 32 so that the auxiliary ICs are connected toand may communicate to ICs connected to the main I²C bus via the normalI²C protocol.

Referring to FIG. 3, there is depicted an exemplary embodiment of asystem for implementing the principles of the present invention. System40 is preferably within a consumer electronic device, such as consumerelectronic device 30 of FIG. 2. System 40 includes main I²C bus/system32, switching circuitry/logic 36, and auxiliary ICs/circuitry/logic 34.

Main I²C bus/system 32 includes main micro 42 that is coupled to a Clockline and a Data line. Within main I²C bus/system 32 are other ICs 44that are connected to the Clock line and the Data line, other I²Cbuses/branches, or the like, 46 that are likewise connected to the Clockline and the Data line, and other I²C devices, generally designated 48that are likewise connected to the Clock line and the Data line.

System 40 is such that the ICs and other components of main I²C system32 operate and/or function in accordance with the standard I²C protocol.System 40 also includes auxiliary ICs/circuitry, generally designated34, that is shown with three auxiliary ICs, namely auxiliary IC 52 (MDDLite Red), auxiliary IC 54 (MDD Lite Green), and auxiliary IC 56 (MDDLite Blue). Auxiliary ICs 52, 54, and 56 provide drive signals togenerate video images on the LCOS display. In this regard, Auxiliary ICs52, 54, and 56 include look up tables for generating the correct lightoutput for each pixel of the imager device. Each LCOS device may includevariations in the imager device that requires each look up table in theassociated EEPROM to include slightly different values. The necessaryvalues may be determined based on, for example, color temperature,imager tolerances, optical tolerances, etc., and may have to bedetermined during manufacture of each LCOS device. The values determinedare then loaded on the EEPROM, and then loaded from the EEPROM onto therespective one of the Auxiliary ICs during start up.

Auxiliary system 34 also contains memory 58, here depicted as a 64KEEPROM. Auxiliary system 34 is I²C compatible by having a Clock line anda Data line that is coupled to each auxiliary ICs and memory. Memory 58contains pre-loaded instructions/data described above that is to beloaded into auxiliary ICs 52, 54, 56, at a data transfer rate which isin excess of the normal I²C data transfer rate or speed. The datatransfer must be completed before operation occurs between the ICs onmain I²C system 32.

System 40 also includes switch/switching circuitry/logic 36 thatincludes switch 50 that may be a CD-4053 CMOS switch, a Control linefrom main IC 42 to switch 50, and a pair of resistors (here 1KΩresistors). The 1KΩ resistors (pull-ups) increases the current in thecircuitry to quicken transition from the low to high state, which isnecessary for proper functioning of the auxiliary ICs during the hightransfer rate mode.

Switch 50 is operative, under the control of main micro 42 (via theControl line) to isolate auxiliary ICs 52, 54, 56 and memory 58 bycoupling the Clock and Data lines of auxiliary system 34 to separateresistors/pull-ups (coupling the Clock and Data lines of the auxiliarycircuit 34 via internal switches to the “0” position in a first, orstart-up, position or mode). Switch 50 is also operative, under controlof main micro 42 to “de-isolate” auxiliary circuitry 34, or connect theClock line of auxiliary circuitry 34 to the Clock line of main I²Ccircuitry 32, and the Data line of the auxiliary circuitry 34 to theData line of the main I²C circuitry 32 (coupling the Clock and Datalines of the auxiliary circuit 34 via internal switches to the “1”position in a second or operating position or mode). In the de-isolatedmode, the Clock and Data lines are coupled to a voltage source (shown as+3.3 volts) through respective resistors (10KΩ each).

During start-up or power-up, main micro 42 sends a control signal (logic“0”) to switch 50 such that the Clock and Data lines of auxiliarycircuit 34 are pulled up to the voltage source (+3.3 volts) through therespective 1KΩ resistors during a low to high transition. The 1kΩresistors, or pull-ups, assist in providing sufficient current tosupport the faster data transfer rate of auxiliary circuit 34. At thistime, auxiliary ICs 52, 54, and 56 can sequentially load data frommemory 58 at a high data transfer rate such as 400 kHz. In the presentLCOS system, each one of Auxiliary ICs 52, 54, and 56 load the data fromEEPROM 58 in sequential fashion. That is, when the reset signal isreceived from main micro 42, a designated one of the auxiliary ICsbegins transferring data from EEPROM 48 at the required rate, i.e., 400kHz. During this period, the designated auxiliary IC acts as the masterIC and generates the necessary clock signals. After a predeterminedperiod of time, when data transfer to the designated auxiliary IC iscompleted, a next one of the auxiliary ICs begins transferring data fromEEPROM 48. The order in which the auxiliary ICs transfer data ishardwired into the ICs. In any event, the auxiliary ICs function as themaster IC for a duration sufficient to transfer all of the required datafrom EEPROM 48. Once sufficient time has elapsed for the data transfer,switch 50 receives a control signal (logic “1”) that now couples theClock and Data lines of auxiliary circuit 34 with main I²C circuitry 32.

FIG. 4 depicts the various signals and their timing relationship for I²Csystem 40 of FIG. 3. In particular, there is depicted power signal 60for I²C system 40, reset signal 62 for auxiliary ICs (52, 54, 56),control signal 64 for switch 50 (from the main micro/IC 42), auxiliaryI²C bus signal 66, and main micro signal 68. Reset signal 62 is alsolabeled MDD Reset correlating to the exemplary embodiment of FIG. 3utilizing the MDD ICs from Three-Five Systems, Inc.

At a point in time, power signal 60 transitions from a low (logic “0”),or OFF, state to a high (logic “1”), or ON state, designated 70.Following the power ON command, reset signal 62 on the Reset line frommain micro 42 goes from a low state to a high state, at point 72.Control signal 64 on the control line from main micro 42 remains in alow state. This signals the proper operating condition for the auxiliaryICs to transfer data at 400 kHz, see the auxiliary bus signal 66 atpoint 78, thus, at this time, auxiliary ICs 52, 54, and 56, cancommunicate with the memory 58 at the faster speed.

During this time, main bus signal 68 can configure (signal portion 82)the remaining ICs on the main I²C bus at the slower I²C speed. Followingthe 500 millisecond wait period 74, main switch 50 connects auxiliaryICs 52, 54, and 56 to main I²C bus and allows main micro 42 tocommunicate with all the ICs connected to the bus. The timingrelationships of the various signals of FIG. 4 show a bus-isolatedportion of the various signals, and a bus common portion of the varioussignals. The bus-isolated portion corresponds to the time period inwhich auxiliary circuit 34 is isolated from main I²C circuit 32, anddata transfer occurs between auxiliary ICs at the higher rate. The buscommon portion corresponds to the time period in which the auxiliarycircuit 34 is de-isolated from the main I²C bus.

Referring now to FIG. 5, there is depicted a flow chart, generallydesignated 90, of an exemplary manner of operation of the presentinvention. In step 92, a power-up, or power-on, signal 60 is generatedand applied to I²C system 40 (point 70 of signal 60 of FIG. 4). Shortlythereafter, in step 94, select ICs are isolated from the main I²C bus.In this case, the isolation is affected by the operation of a switchcoupled between the main and auxiliary I²C bus systems. Following theisolation, main micro 42 provides a LOW to HIGH reset signal 62 on theReset line that is coupled to auxiliary ICs 52, 54, 56. At the LOW toHIGH transition 72 of reset signal 62, the auxiliary ICs communicatewith memory 58 and/or each other (see the signal portion 78 of theauxiliary/isolated I²C bus signal 66 of FIG. 4). Thus, in step 96, theisolated ICs are configured as necessary at the required speed in asequential manner described above. At the same time, main micro 42 keepscontrol signal 64 LOW which causes switch 50 to connect the Clock andData lines of the auxiliary/isolated I²C bus to a voltage through the1KΩ pull-up resistors. Again, the 1kΩ pull-up resistors provide thenecessary current to auxiliary circuit 34 to support a faster datatransfer rate for auxiliary circuit 34.

In step 98, the main I²C bus ICs and associated I²C components areconcurrently configured as represented by the micro I²C signal 68portion 82. After a predetermined time period (here 500 msec) in whichthe auxiliary ICs have time to complete theircommunication/configuration, control signal 64 goes from LOW to HIGH atpoint 76 thereof (see FIG. 4) in order to de-isolate the selected ICs instep 100. Switch 50 thus couples the Clock and Data lines of auxiliaryI²C circuit/bus/portion 34 to the Clock and Data lines of the main I²Cbus. At this point, the circuit transitions from the “bus isolated” modewhere the auxiliary circuit 34 is isolated, to the “bus common” modewhere the auxiliary circuit 34 is part of the main I²C bus portion 32.Thus, both auxiliary I²C bus signal 66 and main I²C bus signal 68 showscommunication at 50 kHz signal portions 80 and 84 respectively. Whilethis invention has been described as having a preferred design, thepresent invention can be further modified within the spirit and scope ofthis disclosure. This application is therefore intended to cover anyvariations, uses, of adaptations of the invention using its generalprinciples. Further, this application is intended to cover suchdepartures from the present disclosure as come within known or customarypractice in the art to which this invention pertains and which fallwithin the limits of the appended claims.

1. A video signal processing apparatus, comprising: an I²C bus havingmain I²C bus portion, a controller IC coupled to said main I²C busportion, an auxiliary I²C bus portion having a plurality of auxiliaryICs connected thereto; and a switch interposed between said main I²C busportion and said auxiliary I²C bus portion and in communication withsaid controller IC, said switch operative under control of saidcontroller IC to selectively isolate said auxiliary I²C bus portion fromsaid main I²C bus portion during a first operating mode of theapparatus, wherein said auxiliary ICs communicate with each other viasaid auxiliary I²C bus-portion at a first data transfer rate, and saidswitch operative under control of said controller IC to selectivelycouple said auxiliary I²C bus portion to said main I²C bus portionduring a second operating mode of the apparatus, wherein said auxiliaryICs communicate with the controller IC via said auxiliary and main I²Cbus portions at a second data transfer rate that differs from the firstdata transfer rate.
 2. The apparatus of claim 1, wherein said firstoperating mode corresponds to a startup mode of the apparatus, and saidswitch is operative under control of said controller IC to isolate saidauxiliary I²C bus portion from said main I²C bus portion for apredetermined period of time during said startup mode.
 3. The apparatusof claim 2, wherein said first data transfer rate is greater than saidsecond data transfer rate.
 4. The apparatus of claim 1, wherein saidswitch comprises an integrated circuit switch.
 5. The apparatus of claim1, further comprising a pair of pull-up resistors coupled to saidswitch; and wherein when said switch selectively isolates said auxiliaryI²C bus portion from said main I²C bus portion, said pull-up resistorsprovide increased current for said auxiliary I²C bus portion.
 6. Theapparatus of claim 1, wherein said auxiliary ICs comprise ICs forgenerating drive signals for R, G, and B signals, and an IC for storinglook up table for generating correct light output for an imager device.7. A television signal receiver comprising: a main I²C bus; a controllerIC in communication with said main I²C bus; a first plurality of I²Ccompatible ICs operatively coupled to said main I²C bus; an auxiliaryI²C bus; a second plurality of I²C compatible ICs operatively coupled tosaid auxiliary I²C bus; and a switch interposed between said main I²Cbus and said auxiliary I²C bus, and in communication with saidcontroller IC, said switch under control of said controller ICselectively isolating said auxiliary I²C bus, and thus said secondplurality of I²C compatible ICs, from said main I²C bus for apredetermined period of time during a startup mode of the secondplurality of I²C compatible ICs, wherein said second plurality of I²Ccompatible ICs communicate with each other via said auxiliary I²C bus ata first data transfer rate, and said switch under control of saidcontroller IC selectively coupling said auxiliary I²C bus, and thus saidsecond plurality of I²C compatible ICs, to said main I²C bus during anoperating mode of the second plurality of I²C compatible ICs, whereinsaid second plurality of I²C compatible ICs communicate with saidcontroller IC via said auxiliary and main I²C buses at a second datatransfer rate that is different than the first data transfer rate. 8.The television signal receiver of claim 7, wherein said second pluralityof I²C compatible ICs comprise ICs for generating drive signals for R,G, and B signals, and an IC for storing look up table for generatingcorrect light output for an imager device.
 9. The television signalreceiver of claim 7, wherein said second data transfer rate is greaterthan said first data transfer rate.
 10. The television signal receiverof claim 7, wherein said switch comprises an integrated circuit switch.11. The television signal receiver of claim 7, wherein isolation of saidauxiliary I²C bus by said switch comprises a first mode for said switch;and said switch has a second mode under control of said master ICwherein said auxiliary I²C bus is part of said main I²C bus.
 12. Thetelevision signal receiver of claim 7, further comprising a pair ofpull-up resistors; and wherein when said switch selectively isolatessaid auxiliary I²C bus from said main I²C bus, said pull-up resistorsprovide increased current for said auxiliary I²C bus.
 13. A method forcontrolling the operation of a video signal processing apparatus havingan I²C bus system, comprising the steps of: providing a switchinterposed between a main I²C bus portion having a main data line and amain clock line, and a controller IC connected thereto, and an auxiliaryI²C bus portion having an auxiliary data line and an auxiliary clockline, and a plurality of auxiliary ICs connected thereto; providing afirst control signal to said switch during a first operating mode ofsaid apparatus for causing said switch to isolate said auxiliary I²C busportion from said main I²C bus portion, and allowing said auxiliary ICsto communicate with each other at a first data transfer rate during saidfirst operating mode, and providing a second control signal to saidswitch during a second operating mode of said apparatus for causing saidswitch to couple said auxiliary I²C bus portion to said main I²C busportion, said auxiliary ICs communicating with said controller IC at asecond data transfer rate that is different from said first datatransfer rate during said second operating mode.
 14. The method of claim13, further comprising the steps of: maintaining the switch in the firstoperating mode for a predetermined period of time when the switchoperates in the first operating mode; and causing the switch to operatein the second operating mode after expiration of the predeterminedperiod of time.
 15. The method of claim 13, wherein the steps ofproviding first and second control signals include the step of: causingthe controller IC in communication with the main I²C bus portion togenerate the control signal.
 16. The method of claim 15, wherein thecontroller IC generates the control signal upon a power-up condition ofthe main I²C bus portion.
 17. The method of claim 15, further comprisingthe steps of: loading data from a look up table for generating thecorrect light output for each pixel of an imager device into theauxiliary ICs during the first operating mode; and generating R, G, Bsignals using the auxiliary ICs during the second operating mode. 18.The method of claim 17, wherein the first data transfer rate is greaterthan the second data transfer rate.
 19. The method of claim 13, furthercomprising the step of: increasing current to the auxiliary I²C busportion during the second operating mode.
 20. The method of claim 19,wherein the step of increasing current to the auxiliary I²C bus portionduring the second operating mode includes the step of: providing aresistor coupled to a power supply for the auxiliary data line and theauxiliary clock line.